UP Xtreme HAT I2C Voltage?
With the HAT in standard mode, what is the voltage of the two I2C ports (pins 3, 5, 27, 28)?
Is it 3v3 like the GPIO or is it 1v8?
Comments
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1.8 V
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@jayman
Where did you find the spec that I2C is 1v8?I found one of your other threads here https://forum.up-community.org/discussion/4248/max-v-cpld#latest
where @rogertsai(AAEON) says that the I2C is 3v3:"Yes, that the current role of the MAX V CPLD is used for CN22 level shift from 1.8V to 3.3V (include I2C)"
Then you say that you "measured" the I2C at 1v8. But as the I2C outputs are open-drain, you must connect a pull-up to get any appreciable voltage swing (I have tested this on an analog scope), so you will see whatever voltage you connected your pull-up resistor to. What we need to know is the input voltage acceptable at SDA - if it's 1v8 logic than 3v3 will be out-of-range, if it's 3v3 then connecting a 1v8 source can be unreliable because the '1' voltage is too low.
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@RFitzgerald said:
@jayman
Where did you find the spec that I2C is 1v8?I found one of your other threads here https://forum.up-community.org/discussion/4248/max-v-cpld#latest
where @rogertsai(AAEON) says that the I2C is 3v3:"Yes, that the current role of the MAX V CPLD is used for CN22 level shift from 1.8V to 3.3V (include I2C)"
Then you say that you "measured" the I2C at 1v8. But as the I2C outputs are open-drain, you must connect a pull-up to get any appreciable voltage swing (I have tested this on an analog scope), so you will see whatever voltage you connected your pull-up resistor to. What we need to know is the input voltage acceptable at SDA - if it's 1v8 logic than 3v3 will be out-of-range, if it's 3v3 then connecting a 1v8 source can be unreliable because the '1' voltage is too low.
This is interesting because I measured the voltage on the I2C pins this morning with a DMM, and I guessed they were 1.8V, too. (Although I measured 5V on I2C0 SDA, but I thought maybe I had the wrong pin). I wasn't using pullups, and I saw the voltage drift up to 1.9V-2.0V on I2C1.
Normal bidirectional open-drain shifters don't work how you're describing. They need to know what Vin_H is in order to know which side is driving the bus. Normally they have a VDDIO input for the high and low side. Sure, they are usually overvoltage tolerant up to 5V, so you can add pullups above VDDIO, but that doesn't define VIL and VIH.
I wish they would provide a schematic for this part of the system. It seems like this question gets asked over and over again, and nobody can give a clear answer. The CPLD definitely has a VDDIO reference for those GPIOs. It wouldn't make much sense to do the I2C at 1.8V and the rest of the GPIOs at 3.3V. If there are no pullups on the 3.3V side, that would explain the ~1.8V measurements, especially when you factor in the drift I saw.
For a definitive answer, you could always trace the I2C pins to the CPLD and check the datasheet to see if that GPIO port has a dedicated VDDIO pin, and if so, measure it. It might be using internal supplies for VDDIO, though, so even that might not be the answer.
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@RFitzgerald wrote:
Then you say that you "measured" the I2C at 1v8. But as the I2C outputs are open-drain, you must connect a pull-up to get any appreciable voltage swing (I have tested this on an analog scope), so you will see whatever voltage you connected your pull-up resistor to. What we need to know is the input voltage acceptable at SDA - if it's 1v8 logic than 3v3 will be out-of-range, if it's 3v3 then connecting a 1v8 source can be unreliable because the '1' voltage is too low.
The pullups are on the UP Xtreme, you don't need pullups on the other side of the HAT connector.
I just connected a logic analyzer to the SCL/SDA pins on the HAT header with nothing else (no slave device or pullups) and it clearly shows that I2C is referenced to 1.8 V and that there are pullups on the main board.
