MAX V CPLD

jaymanjayman New Member Posts: 34

Hey guys, I have several UP Xtreme boards we use for development and prototyping. I was wondering what exactly the role of the MAX V CPLD is. Does it simply level-shift the SPI/GPIO/UART signals between the chipset and the HAT header? I see that I2C is not level-shifted (still at 1.8 V), but all other signals are shifted to 3.3 V, which is actually inconvenient for me since all my peripherals are 1.8 V, so I have to shift it back down. Would be nice if this was programmable somehow. Does the MAX V do anything else other than level-shifting?

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  • rogertsai(AAEON)rogertsai(AAEON) New Member Posts: 228 ✭✭✭

    @jayman
    Yes, that the current role of the MAX V CPLD is used for CN22 level shift from 1.8V to 3.3V (include I2C), and not yet open for other applications. I am just curious to know why do you get 1.8v level on I2C bus (CN22)?

  • jaymanjayman New Member Posts: 34

    Thanks Roger!

    I measured all the signals on the HAT header in the various configurations and I2C @ 1.8 V is what I get :) Which makes sense since I figured you would opt not to level-shift I2C because of the nature of the I2C bus as open-drain with external pull-up, so it can't be level-shifted easily with a simple one-directional buffer like the other busses. When configuring the same pin for GPIO instead of I2C I get 3.3 V, so I was hoping it would be possible for all signals to bypass the level-shifters. Is the MAX V CPLD designed in such a way that it could level-shift from 1.8 V to 1.8 V (essentially implementing a pass-through)?

  • jaymanjayman New Member Posts: 34

    I also had another question about the 3 onboard LEDs. The WIKI states "LEDs [...] are controlled by the pin control CPLD on the board." Can you describe this control mechanism, so I can access the LEDs via GPIO writes to the CPLD?

  • rogertsai(AAEON)rogertsai(AAEON) New Member Posts: 228 ✭✭✭
    edited April 20

    @jayman

    Is the MAX V CPLD designed in such a way that it could level-shift from 1.8 V to 1.8 V (essentially implementing a pass-through)?

    Unfortunately, no, unless HW change, or bypass level shift IC.

    I also had another question about the 3 onboard LEDs. The WIKI states "LEDs [...] are controlled by the pin control CPLD on the board." Can you describe this control mechanism, so I can access the LEDs via GPIO writes to the CPLD?

    As far as i know, this control mechanism is currently only open to Linux, the windows driver is not yet ready (aaeon framework)
    if you're using Ubuntu, you can refer to the below link, to adding a PPA to your system
    https://wiki.up-community.org/Ubuntu#Install_Ubuntu_for_UP.2C_UP_Squared.2C_UP_Core.2C_UP_Core_Plus_and_UP_Xtreme

  • jaymanjayman New Member Posts: 34

    Thanks for the link Roger! I see .deb packages. Can you point me to the source code repository for the UP Xtreme?

    To give you a bit of background, I'm a Windows dev and I write my own drivers for Windows. I'm not using the aaeon framework, I communicate directly with the chipset drivers for I2C, SPI, and GPIO and all of that is working fine. But to access the LEDs I need to go through the CPLD, which in turn is controlled via chipset GPIOs. I'm trying to understand the scheme which chipset GPIOs need to be manipulated in which fashion in order to control the LEDs. Can you help with that, perhaps share the Linux source, I think that's all I need to move forward.

  • jaymanjayman New Member Posts: 34

    Thanks DCleri! Got the LEDs working. Very cool!

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