MAX V CPLD

jayman

Hey guys, I have several UP Xtreme boards we use for development and prototyping. I was wondering what exactly the role of the MAX V CPLD is. Does it simply level-shift the SPI/GPIO/UART signals between the chipset and the HAT header? I see that I2C is not level-shifted (still at 1.8 V), but all other signals are shifted to 3.3 V, which is actually inconvenient for me since all my peripherals are 1.8 V, so I have to shift it back down. Would be nice if this was programmable somehow. Does the MAX V do anything else other than level-shifting?

DCleri

Hi @jayman

The sourcecode is available from the PPA just run sudo apt install linux-source-5.0.0_5.0.0-1.2~upboard4_all.deb

or download it manually from: https://launchpad.net/~aaeonaeu/+archive/ubuntu/upboard/+files/linux-source-5.0.0_5.0.0-1.2~upboard4_all.deb

rogertsai(AAEON)

@jayman
Yes, that the current role of the MAX V CPLD is used for CN22 level shift from 1.8V to 3.3V (include I2C), and not yet open for other applications. I am just curious to know why do you get 1.8v level on I2C bus (CN22)?

jayman

Thanks Roger!

I measured all the signals on the HAT header in the various configurations and I2C @ 1.8 V is what I get Which makes sense since I figured you would opt not to level-shift I2C because of the nature of the I2C bus as open-drain with external pull-up, so it can't be level-shifted easily with a simple one-directional buffer like the other busses. When configuring the same pin for GPIO instead of I2C I get 3.3 V, so I was hoping it would be possible for all signals to bypass the level-shifters. Is the MAX V CPLD designed in such a way that it could level-shift from 1.8 V to 1.8 V (essentially implementing a pass-through)?

jayman

I also had another question about the 3 onboard LEDs. The WIKI states "LEDs [...] are controlled by the pin control CPLD on the board." Can you describe this control mechanism, so I can access the LEDs via GPIO writes to the CPLD?

rogertsai(AAEON)

@jayman

Is the MAX V CPLD designed in such a way that it could level-shift from 1.8 V to 1.8 V (essentially implementing a pass-through)?

Unfortunately, no, unless HW change, or bypass level shift IC.

I also had another question about the 3 onboard LEDs. The WIKI states "LEDs [...] are controlled by the pin control CPLD on the board." Can you describe this control mechanism, so I can access the LEDs via GPIO writes to the CPLD?

As far as i know, this control mechanism is currently only open to Linux, the windows driver is not yet ready (aaeon framework)
if you're using Ubuntu, you can refer to the below link, to adding a PPA to your system
https://wiki.up-community.org/Ubuntu#Install_Ubuntu_for_UP.2C_UP_Squared.2C_UP_Core.2C_UP_Core_Plus_and_UP_Xtreme

jayman

Thanks for the link Roger! I see .deb packages. Can you point me to the source code repository for the UP Xtreme?

To give you a bit of background, I'm a Windows dev and I write my own drivers for Windows. I'm not using the aaeon framework, I communicate directly with the chipset drivers for I2C, SPI, and GPIO and all of that is working fine. But to access the LEDs I need to go through the CPLD, which in turn is controlled via chipset GPIOs. I'm trying to understand the scheme which chipset GPIOs need to be manipulated in which fashion in order to control the LEDs. Can you help with that, perhaps share the Linux source, I think that's all I need to move forward.

jayman

Thanks DCleri! Got the LEDs working. Very cool!

deimos

@jayman , Would you be so kind as to share the windows driver(s) source that you wrote to control the i2c, spi, and gpio? Or at least just the pieces of code that interact with the hardware? I too want to do this! I was under the impression you had to go through the CPLD to control any pins on the HAT (Except maybe the SPI?). This lines up with what DCleri said here and in other posts. Is he wrong and you are able to control a GPIO without talking to the CPLD? Thanks!

jayman

You only need a custom driver if you want to communicate with the MAX V CPLD itself, specifically to control the onboard LEDs.

My upfpga driver exposes an interface that you can call to enable or disable any of the 3 onboard LEDs (resulting in 8 possible states), which is most useful when being called from another driver to visually indicate the status of a device. It's much easier and quicker to glance at the LEDs than sifting through trace logs to obtain a current device status. That driver also had patches to fix a couple issues with previous versions of the UEFI BIOS where some of the direction bits for UART, SPI, and I2S were not being set correctly in the CPLD, but those issues have all been fixed with UEFI BIOS v. 1.9, so those patches are no longer needed.

You do not need any custom drivers to interact with the I2C/SPI/UART/GPIO pins on the HAT header. The requisite I2C/SPI/UART/GPIO controller drivers are all provided by Intel, and the functionality of those interfaces is being abstracted by Microsoft's SpbCx, SerCx2, and GpioClx frameworks, which make it much easier to access and utilize those resources.

deimos

Thank you for the reply! Okay, so the CPLD is really only necessary to control the LEDs? Why do they have an FPGA simply to control 3 LEDS (and level-shifting)? People have talked about wanting to program the CPLD for themselves, but most answers in these forums say they need to contact someone for info on that. I am hoping to figure that info out.

I am hoping to talk to the LEDs myself, as you did. Also, I would find it useful to communicate to the MAX V CPLD itself. I have not programmed CPLD from CPU in a very long time and would appreciate the help. Thanks for the info on this!

DCleri

the CPLD enable a flexible pinctrl management for the LEDs and the 40pin header.

You don't need to do any programming of the CPLD if you want to use the above features, either use the Windows Framework for UP or a supported Linux Kernel to use the I/O.

For a software overview please check the wiki: https://github.com/up-board/up-community/wiki/software_support_overview
More information on the pinout and quick how to for Linux: https://github.com/up-board/up-community/wiki/Pinout_Xtreme

deimos

Can you provide more details on how it provides a flexbile management? jayman above just said you do not need to talk to the CPLD to interact with the "i2C/SPI/UART/GPIO pins on the HAT header". If this is true, what role (specifically, not advertising terms) does the CPLD do here.
Also, my point being I WANT to do CPLD programming. I'm trying to figure out HOW to do that effectively. There have been some posts mentioning reaching out to get potential source and/or instructions, I'm trying to do that.

jayman

Can you provide more details on how it provides a flexbile management? jayman above just said you do not need to talk to the CPLD to interact with the "i2C/SPI/UART/GPIO pins on the HAT header". If this is true, what role (specifically, not advertising terms) does the CPLD do here.

As mentioned before, the CPLD is only used as a level-shifter / buffer / mux for I2C/SPI/UART/I2S/GPIO/ADC to and from the HAT connector. It also controls the 3 onboard LEDs.

If you want to use any of those resources, the CPLD must be configured correctly, but that can be done via BIOS setup, no driver required, unless you need dynamic control in real-time, like I did for the LEDs.

From what I understand, the code that programs the CPLD is contained in the same SPI flash image that contains the UEFI BIOS, so if you wanted to re-program the CPLD you'd have to create a new UEFI BIOS flash image.

Because any CPLD code udpate requires updating the entire platform flash, which also requires a reboot, this is probably not a good development platform for the CPLD.

If you just want to learn CPLD programming and experiment with that I would recommend this instead: https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-max-v.html

Nelli

Can you help with that, perhaps share the Linux source, I think that's all I need to move forward.