MAX V CPLD
Hey guys, I have several UP Xtreme boards we use for development and prototyping. I was wondering what exactly the role of the MAX V CPLD is. Does it simply level-shift the SPI/GPIO/UART signals between the chipset and the HAT header? I see that I2C is not level-shifted (still at 1.8 V), but all other signals are shifted to 3.3 V, which is actually inconvenient for me since all my peripherals are 1.8 V, so I have to shift it back down. Would be nice if this was programmable somehow. Does the MAX V do anything else other than level-shifting?