UART Port IO or MMIO addressing
The UP2 as three UARTs. UART0 is, in theory, a "console" port, while HSUART2 and 3 are, in theory, available for other purposes.
I am trying to use UART0 as a true serial console device that will allow me to access the UEFI Shell. To that end, I have wired up the 10-pin connector to a FTDI serial<->USB converter. From a separate system, I can connect with PuTTY and indeed I get to the UEFI Shell. So far so good.
However, my custom UEFI boot loader, which works on dozens of other x86 platforms, is unable to send output to UART0. In all other systems, I write to the Legacy Port Address 0x3F8 after doing the traditional serial port init squence (setting 115200, N, 8 1). But from what I can determine, the UP2 does NOT support Legacy Port IO. Writes to 0x3F8 do nothing as far as I can tell.
I have switched my UEFI Boot Loader to use UEFI "SerialIO Protocol" and regained access to the UART0. However, my operating system also needs to be able to send output to UART0 and it doesn't have the benefit of using UEFI protocol. No it is NOT Linux or Windows.
So my questions are:
1) Officially, does the UP2 support Legacy Port IO, specifically COM port at 0x3F8 and if so, should I expect to see this on UART0?
2) If the UART0 or any of the HSUARTs have MMIO or Port IO BAR addresses, can anyone tell me what the addresses are? Perhaps if someone is running Windows, they might look at the Device Manager and tell me these resource values?
3) I find both DBGP and DBG2 ACPI tables, both of which 'should' provide the BAR, but both have zero's in the ACPI GAS structures. Yes I am correctly parsing them. Is there something I need to do to enable debug ports on this device?
Thank you thank you thank you if you can help!
Comments
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Nothing? Bummer. Some more info.
Shell> mm 3F8 -w 1 -IO
IO 0x00000000000003F8> : 0xFF > 41
...should have printed 'A' but Legacy Port 3F8 is not present. None of the four Legacy ports are present.I am left not knowing how to address UART0.
Looking into HSUART's 1 and 2. I am able to extract their BAR's from PCI space, but any access to the internal UART registers returns -1.
There is some numbering confusion in the (terribly inadequate spec) about the HSUARTS, so I am not entirely sure which is routed to the HAT connector, but a logic analyzer shows no activity when I try to write to either. Also, the spec doesn't even mention where to find the HSUART pins that are not going to the HAT connector.My conclusion is that neither HSUART is enabled by platform firmware.
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@GMN
UP^2 doesn't support Legacy Port IO.
However, I think you should refer Intel's Slim Bootloader for details, see the link below
https://slimbootloader.github.io/supported-hardware/up2.html?highlight=debug -
MMIO address for COM1 is 0x9152400
