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Interaction between processor and Altera MAX 10 FPGA at UP Squared
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John
New Member Posts: 4 ✭
Hello,
we going to use Up Board Squared. The task is to transfer data to 5 screens (now 320 * 320 * 18bit resolution, we want to have a speed margin when increasing the resolution). There is the possibility of connecting several screens. If they are connected simultaneously, will it work with Up Board Squared? Are there any restrictions? We are interested in the maximum information about the connection of the Altera MAX 10 FPGA and the processor. If the information is classified, we are ready to sign the NDA to obtain the following information:
1. What is the data rate between the Altera MAX 10 FPGA and the processor?
2. SPI:
- How many SPI?
- What is the maximum clock frequency?
- In how many modes (master / slave) can the processor work?
- What is the data transfer width?
3. Is there any parallel interface? If there is, then a maximum of information about it.
4. Do you provide any initial descriptions for VHDL / VERILOG for Altera MAX 10 FPGA for the exchange with the processor?
5. Is there a jtag connector for Altera MAX 10 FPGA?
6. How many Altera MAX 10 FPGA pins are available from the outside?
7. The block diagram shows that the Altera MAX 10 FPGA is USB3.0. Please provide the maximum information about USB 3.0. What is the mechanism for organizing data transfer to FPGA by USB 3.0 exchange rate, etc?
9. What level of drivers does the processor support?
10. Is there a DMA mode for the processor?
we going to use Up Board Squared. The task is to transfer data to 5 screens (now 320 * 320 * 18bit resolution, we want to have a speed margin when increasing the resolution). There is the possibility of connecting several screens. If they are connected simultaneously, will it work with Up Board Squared? Are there any restrictions? We are interested in the maximum information about the connection of the Altera MAX 10 FPGA and the processor. If the information is classified, we are ready to sign the NDA to obtain the following information:
1. What is the data rate between the Altera MAX 10 FPGA and the processor?
2. SPI:
- How many SPI?
- What is the maximum clock frequency?
- In how many modes (master / slave) can the processor work?
- What is the data transfer width?
3. Is there any parallel interface? If there is, then a maximum of information about it.
4. Do you provide any initial descriptions for VHDL / VERILOG for Altera MAX 10 FPGA for the exchange with the processor?
5. Is there a jtag connector for Altera MAX 10 FPGA?
6. How many Altera MAX 10 FPGA pins are available from the outside?
7. The block diagram shows that the Altera MAX 10 FPGA is USB3.0. Please provide the maximum information about USB 3.0. What is the mechanism for organizing data transfer to FPGA by USB 3.0 exchange rate, etc?
9. What level of drivers does the processor support?
10. Is there a DMA mode for the processor?
Comments
-
I can answer some of the questions here:
2) https://up-community.org/wiki/Hardware_Specification_UP2#HAT_CONNECTOR -- 2 SPI, one with 2 chip-select pins, one with 3. Max frequency 25MHz.
3) "Parallel interface" is an ambiguous term.
4) Not their employee, can't answer that.
5) Yes.
6) All of the externally-available pins are connected to the FPGA, see the link above.
7) No, it has literally nothing to do with USB. It's directly connected to the GPIO-pins on the SoC. -
Dear Greeenwood
currently the max10 fpga is only used as a level translator device between Soc gpio and the external connector.
Said so there are many soc peripheral connected to the fpga that can be used as it is on the external hat pin or a custom firmware can be developed in the fpga to implement custom function.
To know more about this please contact aaeon at "customization AT aaeon.eu"
About your other questions:
[ol]
[li]there are many interfaces between the soc and the fpga that can be enabled by request implementing a custom firmware, for example SDIO, SPI, LPC, I2C, UART, GPIO, I2S [/li]
[li]the soc has 3 spi ports connected to the fpga. SPI0 and SPI1 have 2 chip select, SPI3 has 3. The maximum declared speed from intel datasheet is 25mhz but currently due to a bug in the intel driver the maximum safe speed is about 10Mhz. (that could be resolved with some work). The spi support master mode and 0,1,2,3 modes. [/li]
[li]no parallel interface present on the soc sorry. [/li]
[li]for obtaining vhdl/verilog source code you can contact aaeon "customization AT aaeon.eu" [/li]
[li]yes there is a jtag connector and the fpga is also reprogrammable from the cpu[/li]
[li]there are 28 pin exposed on the HAT connector and 20 on the exHAT that are connected directly to the fpga. [/li]
[li]No the fpga is not connected to any usb3 port [/li]
[li][/li]
[li]At the moment "RPi-like" hat functions are supported only in Linux[/li]
[li]The processor on up^2 is an Intel Pentium N4200 or an Intel Celeron N3550 cpu. You can find their specs here or here
[/li]
[/ol]
Best Regards
Nicola Lunghi -
Hello, where can we get the fpga quartus project / source code? The mail bounced back.
-
Dear Nicola,
Can I use DMA for communicating SoC and max10 fpga?
Can I upgrade max10 fpga for more gate?Best Regards,
Jeen -
Hello
Can I use an external graphics card with UP2 via PCI-e x16 to mini PCI-e adapter?
Thanks in advance!
-
@JeenHur said:
HelloCan I use an external graphics card with UP2 via PCI-e x16 to mini PCI-e adapter?
Thanks in advance!
Yes, someone has done that:
https://forum.up-community.org/discussion/comment/7645#Comment_7645
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