So I'd like to debug the Linux kernel, and there seems to be a 10-pin JTAG/SWD connector right behind the USB ports. It this the case? If so, it'd be great to know the compatibility with ots jtag debuggers (J-Link, FTDI-based, also Trace32). In addition OpenOCD and/or T32 scripts would be very welcome.
it is not a JTAG port, it is a UART-debug port (1.8V) connected to CPU but we don't sell any cable for the moment (could be done in the future if there will be more people asking)
Thanks. So is it like uart2? With uart0 on the CN7 and uart1 on the 40-pin GP-bus. Also, is it possible maybe to provide the pinout for this debug UART? I already have a cable that fits as well as a 1.8V ftdi cable.
EDIT: after looking at the UP Connectors Description document, it appears this is indeed a JTAG header and not an uart. I was mistaken, this is a 12-pin instead of 10-pin connector. The doc says CN34 is "Update CPLD Header", so I'm unsure about its purpose. Is there a CPLD/FPGA on the board? I'm thinking this JTAG access, in addition to debugging the kernel, could be used in the case of a BIOS brick.
CN7 has 2x USB2 port and 1xUART-debug port for BIOS debug (you can find the pinout in "TOPIC: CN7 - 1x10P Wafer"
CN34 has CPLD-JTAG port to upload CPLD-fw by cable; You cannot use this port as this will damage the board; this connector has FAN-pwr/ctrl as well.
Thanks aaeon. I probably won't be flashing the CPLD anyway.
What about the second JTAG on the same header? I'm referring to CHT_GPIO_TMS/TDI/TCK/TDO. Does CHT means "chipset", and if correct could it be used to debug the SoC?
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