UP Squared 6000 PCIe lanes and connectors

I am confused a bit User Guide vs Actual implementation - user guide states in one place that M.2 Key M is populated with x2 PCIe lanes while actual slot pinout in the same user guide shows only x1 lane populated. Without schematic my understanding is the following:

1) M.2 Key E - x1 PCIe, x1 USB 2.0
2) M.2 Key B - x1 PCIe, x1 USB 3.0, x1 USB 2.0
3) M.2 Key M - x1 PCIe (or x2 ?)

Can somebody confirm these three point above? Another thing that I really do not get is why designer didn't route at least x1 PCIe lane to this board to board 100pin connector - this will be really cool.