Which periphery can be controlled from Programmable Services Engine (PSE)

MKoestler

As the Pentium/Atom variants of the Up Squared 6000 come with Intel's PSE inside of their Elkhart Lake CPUs, I would be interested in knowing what periphery components can be accessed directly from the PSE.

I am most interested in the GPIO and SPI pins on the HAT40 GPIO header.

Is there any specific documentation for what is possible on the Up Squared or should I consult Intel's documentation for the respective CPU model?

MKoestler

@MKoestler said:
I am most interested in the GPIO and SPI pins on the HAT40 GPIO header.

After giving the "Up Squared 6000 User's Manual" another pass, I realized that the connector descriptions actually include the alternate PSE pin functions (the ones prefixed with PSE_) and that there is at least some serial communication capability with the PSE_I2S1 pins.

However, I did not manage to find out how exactly one is supposed to control which CPU (main core or PSE) drives these pins and if the the PSE's Cortex M7 can simply remap other serial protocol blocks to the pads that are connected.

I realize that this lack of information is not really AAEON's fault, it is just very difficult to find Intel's documentation on the internals of the PSE, so if someone can share some practical experiences or a hint towards how to find the relevant datasheets, that would be much appreciated.

FredyHsu

Hi @MKoestler ,

Please refer to the below link for the documentation. We will release instructions as well. Stay tuned.
https://github.com/intel/pse-fw

Cheers,
UP Team