Request for PCIE and ACPI table information

VMSEAGLE

Is there a layout for the communications port and GPIO registers in PCIe space available. Also, is a specification available for your vendor-specific ACPI tables (and are the COMM and GPIO addresses in them ?).

I am developing drivers for a proprietary non-Windows non-LINUX operating system that will run on the UP2 system. I see that the COMM ports are connected through a FINTEK LPC. I have the I/O space information for the FINTEK but the PCIE side of the connection presents a PCIE configuration table and gets mapped and addressed during the configuration process. What base address register does the PCIE side use ? Are the UART registers available at PCIE MMIO offsets ? Likewise for the GPIO.

I have written a driver for a M.2 board that uses the ASIX AS99100 chip. In addition to providing legacy I/O space access, the PCIE side of the AS991000 provides MMIO access through base address register 1. Using MMIO I can get to the classic 16550 registers as well as enhanced function registers.

Is similar MMIO access through the FINTEK and GPIO connections available ? What are the address offsets in MMIO space ?

camillus

Hi @VMSEAGLE ,

We are checking internally and will get back to you soon.

camillus

Hi @VMSEAGLE ,

For ACPI table, you can use the acpidump tool to get the ACPI information in Linux.

For MMIO or memory layout gpio register kindly refer to our kernel source code .

For our UP kernel 5.4 please refer to pinctrl-broxton.c

If you have an intel account with access to SoC spec, you can also refer to INTEL ApolloLake EDS document for PCEIE memory address.

VMSEAGLE

Sorry - this is not good enough.

First, the operating system I am working with IS NOT Windows or LINUX. It is a different, proprietary operating system. I DO NOT HAVE LINUX INSTALLED.

I am programming to the bear metal. I need register definitions and memory offsets.

I am working on a driver for the embedded COMs ports. I have looked at your drivers as well as everything else I can find on FINTEK LPC chips. I even went to FINTEK for detailed chip specifications (which I did receive). However, all of the FINTEK documentation describes classic I/O space access. No information on PCIE MMIO. Driver source has not helped either.

The INTEL documents will take me as far as their (Intel's) LPC connection. What is behind it (and how is accessed) is dependent on how the pieces are put together. For example, the Atom based board from IBASE uses a different FINTEK chip so what is presented will be different from yours.

YOU ARE THE BOARD MANUFACTURER. If you want people to use your product, then these types of details need to be available.

When I developed my AX99100 serial driver, I executed a non-disclosure and received additional, detailed (and protected) documentation. It was this that allowed me to proceed. I NEED THE SAME INFORMATION FROM YOU ABOUT YOUR VENDOR SPECIFIC IMPLEMENTATION.

Sending me to generic documents DOES NOT TELL ME HOW THINGS LOOK IN THE BOARD THAT YOU PUT TOGETHER ! ! !

I NEED YOUR IMPLEMENTATION DETAILS. (Note I asked for vendor dependent ACPI information).

PLEASE, PLEASE, PLEASE provide what I have asked so I can continue my successful (so far) work.

If you want to continue this discussion privately or execute any needed agreement, here is my contact information:

James Preciado

Senior H.P. Storage, Server and OpenVMS Systems Engineer
H.P. Certified Professional
Brocade Certified Fabric Designer

James J. Preciado, LLC
162 Pascack Road
Hillsdale, NJ, 07642

email: james.preciado@jamespreciadollc.com

camillus

Hi @VMSEAGLE,

Thanks for your email contact, my colleague will contact you soon to follow up on this.

camillus

Hi @VMSEAGLE ,

I have contacted you privately via email.