UP xtreme SPI speed problem

jhp

i have upboard with RT-patch is being used for SPI communication. (more than 6MHz)
(ubuntu16.04, kernel 4.4.86)
link : https://github.com/QiayuanLiao/Ubuntu-RT-UP-Board

recently, I needed a faster operation, so I bought up extreme.
(ubuntu18.04, kernel Linux upxtreme-UP-WHL01 5.0.0-1-generic)
link : https://wiki.up-community.org/Ubuntu_18.04#Install_Ubuntu_kernel_5.0.0_from_PPA_on_Ubuntu_18.04
i expected batter than UPboard. but I can currently communicate with SPI at a speed of 2MHz.
When the communication speed is increased(more than 2MHz), data corruption or shift occur.
I tried applying lowlatency as well, but it failed(same problem).

The development board(STM32F4) is directly connected on the 40pin header, and there is no communication problem in the upboard.

setting value
data length is more than 100byte.
spi mode : SPI_MODE_0
bits per word : 8bits
SPI_IOC_RD_LSB_FIRST : 0x01

DCleri

Please check out this topic for more info: https://forum.up-community.org/discussion/comment/11316

jhp

@DCleri said:
Please check out this topic for more info: https://forum.up-community.org/discussion/comment/11316

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We can confirm that there is an issue with the SPI kernel driver up to version 5.3.4 where you can reach a maximum speed without errors >of 3.6Mbps (when set max speed of 12Mhz)

From kernel 5.3.5 onwards (including 5.4) you can go up to 11.3Mbps (when set max speed of 12Mhz)

We are currently working on upgrading our kernel support to 5.4 LTS (for both Ubuntu and Yocto), which will be available later this year.

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1. i can find only kernel 5.3.0 (https://launchpad.net/ubuntu/+source/linux-hwe-edge/5.3.0-24.26~18.04.2).
   let me know any other link?

DCleri

there is a kernel 5.4: https://packages.ubuntu.com/bionic/linux-generic-hwe-18.04-edge

but it doesn't include our patches for pincontrol, we are currently working on it and we expect to have it released in early Q4

jhp

i use low latency kernel now (Linux upx-UP-WHL01 5.0.8 #3 SMP PREEMPT Tue Aug 25 17:56:31 KST 2020 x86_64 x86_64 x86_64 GNU/Linux )
When viewed through an oscilloscope, I found that the clock stopped in the middle at a setting of 13MHz or higher.
Because of this, communication errors(shift, change, loss) are occurring, and there is a limit to speeding up the communication speed.

Will this problem be solved in the currently produced kernel? (kernel 5.4)
I have to send and receive more than 150 bytes of data per cycle with a clock of more than 20MHz and a cycle of less than 500us.

jhp

When looking at the time between the point where the CS pin goes low and the point where the clock starts, it can be seen that the UP board takes 28us time at 12MHz clock and the UP xtreme takes 0.48us time at the same clock.
It was confirmed that the time of UP board was similar regardless of clock, but UP xtreme decreased to 0.25us.
If a program is created using CS interrupt, it can be seen that there is a problem in data catching due to a short time of 0.48us in UP xtreme.
To fix this, I am wondering if there is a way to adjust the time until the clock starts after the CS pin goes low.