DOCKING II (CN26) header

jayman
jayman New Member Posts: 66 ✭✭
in UP Xtreme Hardware Specification

Had a couple questions about the signals on the DOCKING II (CN26) header:

  1. Am I correct to assume that SLP_S3# (pin 1) connects to SUS_STAT# on the chipset?
  2. Do pins 19/21 connect directly to the I2C4 port on the chipset?
  3. Do pins 18/20 connect directly to the SMBus controller on the chipset?
  4. What is the origin of the STACK_GPIO[1:7] signals? Do they connect to the chipset or the SIO chip? If chipset, what is the mapping for those pins?

As far as the actual 30-pin connector, do you offer a cable that mates with that connector in order to access these signals? Or do we need to build our own? What's the part number for the mating connector?

Actually I had the same question about the USB connector (CN16). Do you offer some kind of cable or adapter that fits that socket? If not, what's the part number of the mating connector?

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  • jayman
    jayman New Member Posts: 66 ✭✭
    edited July 2020

    @jayman said:
    1. Am I correct to assume that SLP_S3# (pin 1) connects to SUS_STAT# on the chipset?

    Disregard that one. SLP_S3# belongs to the PMC, not the LPC, sorry.

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  • jayman
    jayman New Member Posts: 66 ✭✭

    Any thoughts or info on this?

    @jayman said:
    Had a couple questions about the signals on the DOCKING II (CN26) header:

    1. Do pins 19/21 connect directly to the I2C4 port on the chipset?
    2. Do pins 18/20 connect directly to the SMBus controller on the chipset?
    3. What is the origin of the STACK_GPIO[1:7] signals? Do they connect to the chipset or the SIO chip? If chipset, what is the mapping for those pins?

    As far as the actual 30-pin connector, do you offer a cable that mates with that connector in order to access these signals? Or do we need to build our own? What's the part number for the mating connector?

    Actually I had the same question about the USB connector (CN16). Do you offer some kind of cable or adapter that fits that socket? If not, what's the part number of the mating connector?

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  • jayman
    jayman New Member Posts: 66 ✭✭

    Still curious about the STACK_GPIO[1:7] signals on CN26. Can you clarify what they connect to on the chipset?

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  • DCleri
    DCleri Administrator, AAEON Posts: 1,213 admin
    edited October 2020

    they are connected directly to the SoC GPIOs like all the other signals and at 1.8V level (except the power signals)

    The only connector that we make available is the one to connect CN26 with the carrier board (e.g. Net Plus) as those extra signals are needed for the correct functionality of the 2 boards together

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  • jayman
    jayman New Member Posts: 66 ✭✭
    edited October 2020

    Thanks @DCleri! Can you provide the mapping of the STACK_GPIO[7:1] pins to PCH GPIO pins please?

    The WHL EDS doesn't make any mention of "STACK_GPIO" so it's not clear to me what those pins are actually connected to. Does that refer to ISH_GP[7:1} or something else?

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  • RFitzgerald
    RFitzgerald New Member Posts: 6 ✭

    I also want to know what the STACK_GPIO[7:1] signals map to. I need some GPIOs that I can use when the HAT is in AAM mode.
    @jayman has asked several times in this thread, but there's no answer yet.

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  • jayman
    jayman New Member Posts: 66 ✭✭

    I would also like to bring this question back to the top. Would greatly appreciate some answers!

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  • DCleri
    DCleri Administrator, AAEON Posts: 1,213 admin

    Please see the information provided by Roger on this topic: https://forum.up-community.org/discussion/4574/change-acpi-tables-to-add-hid-over-i2c-device#latest

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