I2S_CLK and I2S_FRM direction setting not working

jaymanjayman New Member Posts: 28

Configuring I2S_CLK and I2S_FRM in the BIOS settings doesn't seem to have any impact on the actual pin configuration:

Regardless of whether those pins are configured as input or output, they will always behave as inputs, i.e. it appears the selection from the BIOS settings is not transferred to the MAX V FPGA:

00000220 ::: UP Xtreme FPGA: Platform ID = 0101, Firmware ID = 1020, Func En = 4300, GPIO Dir = 068362b7
00000221 ::::: UP Xtreme: HAT pin 7 [ADC0] configured as pass-through.
00000222 ::::: UP Xtreme: HAT pin 27 [I2C0_SDA] configured as pass-through.
00000223 ::::: UP Xtreme: HAT pin 28 [I2C0_SCL] configured as pass-through.
00000224 ::::: UP Xtreme: HAT pin 3 [I2C1_SDA] configured as pass-through.
00000225 ::::: UP Xtreme: HAT pin 5 [I2C1_SCL] configured as pass-through.
00000226 ::::: UP Xtreme: HAT pin 19 [SPI_MOSI] configured as output.
00000227 ::::: UP Xtreme: HAT pin 21 [SPI_MISO] configured as input.
00000228 ::::: UP Xtreme: HAT pin 23 [SPI_CLK] configured as output.
00000229 ::::: UP Xtreme: HAT pin 24 [SPI_CS0] configured as output.
00000230 ::::: UP Xtreme: HAT pin 26 [SPI_CS1] configured as output.
00000231 ::::: UP Xtreme: HAT pin 8 [UART1_TX] configured as output.
00000232 ::::: UP Xtreme: HAT pin 10 [UART1_RX] configured as input.
00000233 ::::: UP Xtreme: HAT pin 11 [UART1_RTS] configured as output.
00000234 ::::: UP Xtreme: HAT pin 36 [UART1_CTS] configured as input.
00000235 ::::: UP Xtreme: HAT pin 12 [I2S_CLK] configured as input.
00000236 ::::: UP Xtreme: HAT pin 35 [I2S_FRM] configured as input.
00000237 ::::: UP Xtreme: HAT pin 38 [I2S_DIN] configured as input.
00000238 ::::: UP Xtreme: HAT pin 40 [I2S_DOUT] configured as output.
00000239 ::::: UP Xtreme: HAT pin 13 [GPIO5] configured as input.
00000240 ::::: UP Xtreme: HAT pin 15 [GPIO6] configured as input.
00000241 ::::: UP Xtreme: HAT pin 29 [GPIO11] configured as output.
00000242 ::::: UP Xtreme: HAT pin 31 [GPIO12] configured as output.
00000243 ::::: UP Xtreme: HAT pin 33 [GPIO13] configured as output.
00000244 ::::: UP Xtreme: HAT pin 37 [GPIO15] configured as input.
00000245 ::::: UP Xtreme: HAT pin 16 [GPIO19] configured as output.
00000246 ::::: UP Xtreme: HAT pin 18 [GPIO20] configured as output.
00000247 ::::: UP Xtreme: HAT pin 22 [GPIO21] configured as output.
00000248 ::::: UP Xtreme: HAT pin 32 [GPIO25] configured as output.

I also took electrical measurements to confirm that I2S_CLK and I2S_FRM are configured as inputs.

Am I doing something wrong or is this an issue with the BIOS?

Comments

  • DCleriDCleri Administrator, AAEON Posts: 1,014 admin

    We are currently investigating, but it is most likely a BIOS issue.

    At the moment we are in the process of releasing a new BIOS which will enable a new feature (called Advanced Audio Mode) which will enable more audio pins to be used including another I2S signal (but at different voltage level, only 1.8V).

    Any additional fix (for example if we confirm the above issue) will be included in a future BIOS release.

  • jaymanjayman New Member Posts: 28

    Thanks for the update! Looking forward to the BIOS update. Do you have an ETA for that?

    FPGA passthrough from the chipset at VL = 1.8 V is really more convenient for me anyways since all modern peripherals operate at that lower level to begin with.

    PS: I'm able to work around the original issue by re-programming the FPGA in my own UP FPGA driver, but I wanted to bring it to your attention so it can be fixed for the rest of the world :smile:

  • DCleriDCleri Administrator, AAEON Posts: 1,014 admin

    It is not a problem of the FPGA, but the BIOS option that do not set the correct value even when changing the setting from the menu.
    The FPGA has only a logic to send-receive commands and muxing, but those value are set at SoC level.

    Regarding the new BIOS release, most likely next week.

  • mattowenmattowen New Member Posts: 2
    edited July 21

    @DCleri said:
    It is not a problem of the FPGA, 8 ball pool but the BIOS option that do not set the correct value even when changing the setting from the menu.
    The FPGA has only a logic to send-receive commands and muxing, but those value are set at SoC level.

    Regarding the new BIOS release, most likely next week.

    That was it, Thank you

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