ACPI table entries for HSIC and I2C

allsey87allsey87 New Member Posts: 17

Hello, is there any need to provide ACPI table entries to enable the HSIC and I2C interfaces on the exHAT connector? Or are these enabled by default?

Comments

  • garywgaryw New Member, Moderator, AAEON Posts: 29 admin

    for Windows 10, you need install Up Framework SDK and refer UpDemoApp to see how to using UpBridge to access GPIO or I2C. https://downloads.up-community.org/download/up-sdk-for-windows-10-and-windows-iot/

    for Ubuntu you need update kernel image for Up https://wiki.up-community.org/Ubuntu#Install_Ubuntu_kernel_4.15.0_for_UP_from_PPA_on_Ubuntu_16.04
    then you can refer Up WiKi to check GPIO and I2C https://wiki.up-community.org/UP_Core_carrier_board_(low_speed_I/O)

  • allsey87allsey87 New Member Posts: 17

    @garyw unfortunately that does not answer my question for a number of reasons.
    1. I am using Yocto, not Windows 10 nor Ubuntu
    2. The link to the low speed carrier board does not contain any information regarding ACPI table entries.

    I am looking for reference material on the ACPI table entries for HSIC and I2C (assuming they are required). As an example, an ACPI table entry looks something like this: https://github.com/AAEONAEU-SW/meta-up-board/blob/sumo/recipes-bsp/acpi-tables/spidev1.0.asl

  • garywgaryw New Member, Moderator, AAEON Posts: 29 admin

    Sorry for misunderstand your question, you can check attached ACPI table for CRST02 carrier board

  • allsey87allsey87 New Member Posts: 17

    Great! Could you also attach the ACPI table for the CRST01 carrier board?

  • garywgaryw New Member, Moderator, AAEON Posts: 29 admin
    edited February 20

    sorry for reply late, checked with BIOS developer, there are no ACPI table in CRST01.

  • allsey87allsey87 New Member Posts: 17

    Hi @garyw, still working on this without any real progress towards getting HSIC working on my carrier board.

    To the best of my knowledge, crst02.txt contains the SSDT entry which would be compiled with iasl and loaded onto the EERPOM following the UP Core Carrier Board EEPROM specification. So far, I have only found what appears to be GPIO mappings for the FPGA on the CRST02 carrier board, but nothing regarding the configuration of I2C or HSIC.

    So my question would be:

    Should a SSDT entry be provided on the EEPROM to enable the HSIC interfaces for a carrier board? If not, how should these interfaces be enabled?

  • DCleriDCleri Administrator, AAEON Posts: 998 admin

    They are not required for HSIC (USB/PCIe) or I2C.

    If you are using our carrierboard which interfaces the SoC I/O via FPGA, you need to add those information in the ACPI table.
    If you connect directly to the SoC I/O you can control them directly from sysfs or other standard kernel interface.

    You have posted under UP Core carrier boards and you are mentioning exHAT.

    Can you please explain what is your platform and what you are trying to achieve?

  • allsey87allsey87 New Member Posts: 17

    Thanks for the reply @DCleri, we have a custom carrier board with two USB3503 hubs connected to HSIC1 and HSIC2. For the moment, when I check the boot messages¹ with dmesg and inspect the USB devices with lsusb on the attached Up Core, I can only see the two inbuilt USB hubs. I am trying to understand whether it is necessary to set the pin modes or to declare these USB hubs in the ACPI / EEPROM configuration somewhere.

    ¹ I am testing with the latest kernel from Arch Linux booted using the EFISTUB method (incl. Intel microcode). Perhaps there is some ACPI configuration in the initrd that I am missing?

  • DCleriDCleri Administrator, AAEON Posts: 998 admin

    Hi @allsey87

    I am sorry but we cannot support issues on Arch Linux and a custom kernel and the EFISTUB method for boot.
    Can you please test it on our supported distribution and provide the logs?

    We have our carrier boards with USB hubs and interfaces on I2C (eeprom) and they are visible from the OS automatically.
    Can you confirm you have implemented the carrier board following the design guide we provided?
    https://up-shop.org/media/productattach/u/p/up_core_carrier_board_design_guide_20171116_2_.zip
    https://up-shop.org/media/productattach/u/p/upcore_eeprom_spec_v1.0.pdf

  • allsey87allsey87 New Member Posts: 17

    Hi @DCleri , thanks again for your response.

    I can confirm that I read through the carrier board design instructions during the design of our PCB and have included an EEPROM on the board, although it is currently blank since, to the best of my knowledge, this is only for ACPI configuration of which we don't have any for the moment.

    From the website, it seems the two officially supported kernels are the one built from Yocto and a custom Ubuntu kernel. Are the patches etc. for the custom Ubuntu kernel (linux-upboard-lts-xenial) available online? I tried digging through launchpad to find them without much luck.

    One last question, do both of the kernels (i.e., from Yocto (sumo) and from Ubuntu) support the high-speed carrier board?

  • DCleriDCleri Administrator, AAEON Posts: 998 admin
    edited June 8

    There is no need of specific Kernel patches to support the high speed carrier board, but all our tested distributions are using a standard Grub with the kernels provided.
    Please make sure you test that configuration first so we have a common starting point.

    The patches are mainly for the 40pin header (and low speed carrier board) and other minor bugfixes for specific drivers.
    You don't need to add anything extra to your kernel, but just use a standard Ubuntu distribution and kernel (either 4.15 or 5.0) which have both been tested.

    The patches for latest Yocto supported kernel are: https://github.com/AAEONAEU-SW/meta-up-board/tree/warrior-dev/recipes-kernel/linux/files
    The source code of the modified Ubuntu kernel can be downloaded from the PPA: https://launchpad.net/~aaeon-cm/+archive/ubuntu/upboard/+files/linux-source-5.0.0_5.0.0-1.2~upboard5_all.deb

    Also I suggest you to create and flash the EEPROM as per instructions even if with just description values (of the carrier board).

  • allsey87allsey87 New Member Posts: 17

    Hi @DCleri, just to make sure we are starting from the same point, can you tell me exactly which version of Ubuntu you would like installed? For example 18.04.4 LTS or 19.04 and which variant: desktop or server? I know this shouldn't matter, but if we want a common starting point we might as well be precise about it.

    Regarding the initialising the EEPROM, could you tell me which of the following devices correspond to the I2C0_SOC_SXX and I2C1_SOC_SXX pins on the 100-pin header?

    i2cdetect -l
    i2c-0   i2c         Synopsys DesignWare I2C adapter     I2C adapter
    i2c-1   i2c         Synopsys DesignWare I2C adapter     I2C adapter
    i2c-2   i2c         Synopsys DesignWare I2C adapter     I2C adapter
    i2c-3   i2c         Synopsys DesignWare I2C adapter     I2C adapter
    i2c-4   i2c         Synopsys DesignWare I2C adapter     I2C adapter
    i2c-5   i2c         Synopsys DesignWare I2C adapter     I2C adapter
    i2c-6   i2c         i915 gmbus ssc                      I2C adapter
    i2c-7   i2c         i915 gmbus vga                      I2C adapter
    i2c-8   i2c         i915 gmbus panel                    I2C adapter
    i2c-9   i2c         i915 gmbus dpc                      I2C adapter
    i2c-10  i2c         i915 gmbus dpb                      I2C adapter
    i2c-11  i2c         i915 gmbus dpd                      I2C adapter
    i2c-12  i2c         DPDDC-D                             I2C adapter
    
  • DCleriDCleri Administrator, AAEON Posts: 998 admin

    We have a wiki with instructions setup and additional steps for kernel, wifi/bt firmware, etc.: https://wiki.up-community.org/Ubuntu_18.04

    Desktop I believe it would be easier if you need to test also WiFi

    i2cdetect numbers are not consistent and can vary.
    Please use the design guide to write the eeprom code: https://up-shop.org/media/productattach/u/p/upcore_eeprom_spec_v1.0.pdf

  • allsey87allsey87 New Member Posts: 17

    So I think found the issue, one of our engineers has mirrored the connection between the two PCBs. We will need to redesign our board I think. Quick question regarding the EEPROM and ACPI tables: Does the standard BIOS on the Up Board (not Up Core), also check the EEPROM at 0x50-0x53 and load SSDTs from this memory?

  • DCleriDCleri Administrator, AAEON Posts: 998 admin

    no it doesn't
    It is a feature available only on UP Core and UP Core Plus.

  • allsey87allsey87 New Member Posts: 17

    Ok, thank you for your patience and support @DCleri

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