Interaction between processor and Altera MAX 10 FPGA at UP Squared

JohnJohn Posts: 4New Member
we going to use Up Board Squared. The task is to transfer data to 5 screens (now 320 * 320 * 18bit resolution, we want to have a speed margin when increasing the resolution). There is the possibility of connecting several screens. If they are connected simultaneously, will it work with Up Board Squared? Are there any restrictions? We are interested in the maximum information about the connection of the Altera MAX 10 FPGA and the processor. If the information is classified, we are ready to sign the NDA to obtain the following information:

1. What is the data rate between the Altera MAX 10 FPGA and the processor?

2. SPI:
- How many SPI?
- What is the maximum clock frequency?
- In how many modes (master / slave) can the processor work?
- What is the data transfer width?

3. Is there any parallel interface? If there is, then a maximum of information about it.

4. Do you provide any initial descriptions for VHDL / VERILOG for Altera MAX 10 FPGA for the exchange with the processor?

5. Is there a jtag connector for Altera MAX 10 FPGA?

6. How many Altera MAX 10 FPGA pins are available from the outside?

7. The block diagram shows that the Altera MAX 10 FPGA is USB3.0. Please provide the maximum information about USB 3.0. What is the mechanism for organizing data transfer to FPGA by USB 3.0 exchange rate, etc?

9. What level of drivers does the processor support?

10. Is there a DMA mode for the processor?


  • luigiluigi Posts: 3New Member
    edited August 2017

    to connect 5 screen to UPsquared you have:
    1. HDMI port
    2. DP port
    3. eDP port

    in addition you can use 3x USB3 port all NATIVE ports from CPU (no HUB) to which you can connect USB3-to-HDMI adapter.
    This is the fastest and easiest solution.

    As alternative, you have Mini-PCIe connector (x1 PCIe.Gen2) to which you could connect a video card or a Cyclone FPGA integrating a Video Controller

    All these info is available from Datasheet

    MAX10. The CPU.port connected to MAX10 are shown on DataSheet (1xUART, 2xI2C, 1xSPI, 1x I2S, 2xPWM, 8xGPIOs) for the model integrating APL-I Atom (available end of 2017) there will be an additional CPU.SPI port and CPU.SDIO port connected. The SDIO has higher bw (100MB/s) which is the max data rate between CPU and FPGA
    MAX10 is connected to HAT_connector and EXHAT_connector with 3V3 TTL

    SPI. on current version there is a single SPI.port rated 25Mbit/s on APL-I (Atom, available end of 2017) there will be a second SPI.port

    Parallel interface. On EXHAT_conn we integrated an LVDS.port 3V3 from MAX10 (8 differential data-lanes +1x differential PLL_IN +1x differential PLL_OUT) which has not been tested yet

    FPGA-CPU interface. We don't provide any SDIO-slave IP nor SPI-slave IP although MAX10 can support both of them. Customer should purchase and integrate IP and RTL. We are in favor to support FPGA projects but Customer has the full responsibility of FPGA FW development and integration. All what we do is provide the Quartus DB needed to program MAX10

    JTAG. Yes, the FPGA can be programmed using MAX10.JTAG port

    Please check better the block diagram; there is NO USB3 nor USB2 bus connection between CPU and MAX10; we could do this for a Custom project (contact sales) if you want but you need to make an order of 2K pcs minimum.

    Drivers. APL CPU is fully supported by Intel YOCTO Linux, so you will get ALL DRIVERs for all exposed ports under Linux. We are also working with Microsoft for full driver support on Windows10

    DMA. there are two, 8-channel universal DMA interfaces for transferring data between memory
    buffers and peripherals and between memories. Not all peripherals has DMA so you need to test the processor to check that DMA efficiency is satisfactory for you application.
  • johanterjohanter Posts: 2New Member

    About the comment "All what we do is provide the Quartus DB needed to program MAX10"
    Where do we get this quatrus DB.

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