FPGA details

Can you share more about the MAX 10 FPGA on the UP^2 board?

Which density part will be used, e.g. 10M02, 10M04, ...?

Will the FPGA development be carried out in an open-source way, so that interested makers can modify the HDL to add or modify the expansion features?

More generally, can you say anything about your vision for open development in the UP^n ecosystem generally? For example, will you publish a schematic for the board at some point? This would make it more appealing for advanced users.

Thanks.

Comments

  • Mark HaunMark Haun Posts: 2New Member
    edited March 2017
    So I guess the AAEON folks aren't reading their own forum. Hopefully this is because they're so busy getting UP^2 ready for production! :)

    But anyhow, I was perusing the UP^2 Kickstarter page when I discovered that my question has already been answered (it's the second FAQ entry):

    https://www.kickstarter.com/projects/802007522/up-squared-the-first-maker-board-with-intel-apollo/faqs

    tl;dr: It's the 10M02, as expected--FPGA parts are expensive and even this one has a nontrivial impact on the BOM cost. It would be cool if, in the future, they find a way to sell a "premium" board with a 10M16.

    I wanted to highlight one part of the FAQ answer, and ask a follow-up question:
    IN THE FUTURE, user will be able to upload custom fw inside the FPGA; IN THE FUTURE, we will open a special section on UP-community but today there is no plan on when this will be done. We cannot do it immediately as in case of wrong design, the board could be damaged so we have first to find a "safe design flow"

    This is encouraging to me, but also worrisome. Encouraging, because it acknowledges the FPGA programmability could be a selling point for hobbyists who want to implement new interfaces. Worrisome, because (a) "wishlist" items like this usually do not happen at all, despite good intentions; and (b) it sounds like you might not be ready to open up the design enough for your technically competent customers to contribute.

    Please remember that your audience includes people with just as much knowledge and experience as the members of the UP^2 technical team. You should be treating us as technical resources, an extension of your own team, not as electronics beginners to be taught and protected. And the best part is, this way you get some work done for free :) Obviously, your audience includes beginners too, but isn't it enough to warn "proceed at your own risk" and leave it at that? (Anyway, I don't see how you can *ever* manage to make FPGA development "safe" on this board, assuming that you give full access to generate our own bitstreams. It's inherently risky.)

    I hope AAEON will place the complete VHDL or Verilog sources on Github so the community can assist them in opening up this exciting new dimension of the UP boards. It would be even better if the board design files (at a minimum, the schematic diagram) could be made available too. This is very common for the ARM boards that you are competing against.

    Regards,
    Mark
  • FabrizioFabrizio Posts: 123AAEON mod
    Hi,

    sorry for the delay but we were super busy with UP Squared, tradeshow ( 4 tradeshows in 2 weeks ) and UP Core announcement.
    We are working on this topics and probably we will open the code and let the people modify.
    We have had a discussion with a potential partner who can support all the community.
    As soon as the board will be on the market ( May/June ) the problem should be solved.
    All the best
    Cheers
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