Confusion about number of SPIs

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nukular
nukular New Member Posts: 61 ✭✭✭
in UP Squared Linux

Hi,

In the specifications for the Up2 it says there are two SPI busses on the HAT connector: SPI0 with 2 CS and SPI1 with 3 CS.

However, only SPI0 is listed in the pin configuration and that's also the only one available in /dev/ (where it is called spidev1.x for some reason).

What's with the other SPI? Are there just no drivers, or is it really not exposed on the HAT (if so, why is it listed in the wiki)?

Is there some way to get a second SPI bus working on the HAT (or exHAT)? Other than doing software SPI of course.

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  • Troy Lin
    Troy Lin Guest Posts: 33 ✭✭
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    Hi Nukular,

    The UP2 board with N3350 & N4200 does only have one SPI to the 40 pins, with the later E3940 also will be the same. The reason can be explained better with below cut out from Intel Apollo Lake specification on SPI.

    As you can see from the note: N series CPU only support SPI0 to be used. E series CPU does have 3x SPI, however, we are using 1x SPI for ADC function and 1x SPI to the exHAT connector, which only leave 1x SPI for the 40 pins.

    I hope this is clear for you and everyone on why only 1x SPI is available on the 40 pins.

    Thank you.

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  • nukular
    nukular New Member Posts: 61 ✭✭✭
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    Ok, thanks for the clarification Troy.
    Maybe it would be good idea to change that in the specifications page on the Wiki then?

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  • Troy Lin
    Troy Lin Guest Posts: 33 ✭✭
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    Hi Nukular,

    Yes, it is a good idea to update the WIKI to avoid misleading information
    I will look into it

    Thank you.

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