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UP Board - SPI sustained data rate (<1MB/s) ?
Jason Lessenger
New Member Posts: 1 ✭
Hello,
I am using an UP board with an output device connected to the SPI pins (SPI_CLK and SPI_MOSI).
I am using SPI with DMA transfers (via the pxa2xx* diver)
I have found that I am limited to ~830KBytes/Sec - regardless of SPI clock rate.
This is even using just a single DMA transfer buffer.
I read that up to 25MHz clock was supported =>~3MB/s , so I suspected some issue in the driver.
I attached a Logic Analyser to check it and found that the clock rate *is* honored.
(e.g. If I select 12.5MHz then I *do* see CLK running 12.5MHz)
However, this is not sustained within a single DMA transfer.
i.e. There is reduced utilization - that is, periods where CLK just stops!
At 4MHz I see nearly 100% utilization, reducing at 8MHz and even further at 12.5MHz.
This accounts for the throughput limitation.
I did some searching and found a Z8000 series datasheet that says the SPI is running over the SSP
and the SSP itself is limited to 6.5Mbps (832KB/s).
Are my findings correct?
Is there any way to lift this limit (I'm trying to achieve 8Mbps minimum)?
Or, would I need to forgo the hardware SPI and bit bash on some other GPIO? (Is that even possible?)
I welcome any insight in this area.
Regards.
J Lessenger.
I am using an UP board with an output device connected to the SPI pins (SPI_CLK and SPI_MOSI).
I am using SPI with DMA transfers (via the pxa2xx* diver)
I have found that I am limited to ~830KBytes/Sec - regardless of SPI clock rate.
This is even using just a single DMA transfer buffer.
I read that up to 25MHz clock was supported =>~3MB/s , so I suspected some issue in the driver.
I attached a Logic Analyser to check it and found that the clock rate *is* honored.
(e.g. If I select 12.5MHz then I *do* see CLK running 12.5MHz)
However, this is not sustained within a single DMA transfer.
i.e. There is reduced utilization - that is, periods where CLK just stops!
At 4MHz I see nearly 100% utilization, reducing at 8MHz and even further at 12.5MHz.
This accounts for the throughput limitation.
I did some searching and found a Z8000 series datasheet that says the SPI is running over the SSP
and the SSP itself is limited to 6.5Mbps (832KB/s).
Are my findings correct?
Is there any way to lift this limit (I'm trying to achieve 8Mbps minimum)?
Or, would I need to forgo the hardware SPI and bit bash on some other GPIO? (Is that even possible?)
I welcome any insight in this area.
Regards.
J Lessenger.
Comments
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Hi, @Jason%20Lessenger
I use MRAA driver for SPI and find that it will generate interrupts every 8 bit, so I guess DMA would help.
You said that you can use SPI with DMA via pxa2xx driver. Do you have any tutorials or examples or reference links that I could check?
It's quite difficult to use DMA under X86 rather than ARM platform. -
Hi, @Jason%20Lessenger
I think you are right.
I found "This enables using a PXA2xx or Sodaville SSP port as a SPI master controller. The driver can be configured to use any SSP port and additional documentation can be found a Documentation/spi/pxa2xx."
