GPIO-control via Linux mmap-interface?
WereCatf
New Member Posts: 201 ✭
The Linux GPIO sysfs-interface is excruciatingly slow and limited, only useable for the most basic stuff, and even then just barely. On ARM-devices I use the Linux mmap-interface to directly access the various GPIO-registers to set them up as I like and to toggle them, reaching several tens of times faster I/O-speeds than one could ever achieve via the sysfs-interface. Alas, how does one operate the registers on Intel platform? I've never done anything like that on an Intel-device and it's difficult to even find any documentation on the registers, let alone how to manipulate them.
Comments
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The GPIO controller registers are documented in this data sheet:
https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-2.pdf
Performance is limited by reads to the GPIO controller registers, which are very slow (~25 microseconds, iirc) for some reason. If you can avoid reading those registers when changing GPIO output states, you may achieve higher speeds for driving GPIO outputs with direct register access.
Regarding direct register access, one thing to be aware of is that there's a nasty bug on the GPIO controller implementation on this chip which means that you must prevent concurrent accesses to the GPIO controllers from multiple threads. So if, for example, you implement a user-space library that accesses the GPIO registers directly, make sure to disable the GPIO driver in the kernel and make sure that only one application thread can access the GPIO registers at any time. -
The PDF you linked to is for the SoC on the Up1, does it apply as-is to the Up^2 SoCs, too?
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Oops, sorry, I didn't spot that this was posted under an UP^2 topic. Sorry about that. I don't have a link to a publicly-accessible datasheet for the Apollo Lake SoC on UP^2, but the kernel driver would be a good source of information here:
This file mostly just defines the GPIO pins on the APL SoC:
http://elixir.free-electrons.com/linux/latest/source/drivers/pinctrl/intel/pinctrl-broxton.c
The logic to manage the GPIO controller registers can be found here:
http://elixir.free-electrons.com/linux/latest/source/drivers/pinctrl/intel/pinctrl-intel.c -
Has anyone found out if this is possible? GPIO performance would be pretty important for my application.
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Hi @machinekoder ,
That depends on GPIO performance you need for your application. But UP2 should be Ok for most of the applications...
Cheers!
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@ccalde The 5us write time per pin indicated by @nukular here https://forum.up-community.org/discussion/comment/8941#Comment_8941 would be too much for my application.
